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ai-infrastructure

Compute Was Never the Bottleneck — Moving Bits Is

Compute Was Never the Bottleneck — Moving Bits Is

The thesis in one breath * Compute scaled ~60,000× in 20 years; the wires feeding it did not. * The binding constraint on modern AI accelerators is moving bits — and it is one problem whether it happens between GPU↔GPU (the network) or GPU↔memory (the HBM bus), because both cross

Vera Rubin Decoded Pt. 6 | Supply Chain - Master Reference

Vera Rubin Decoded Pt. 6 | Supply Chain - Master Reference

⚠️ Educated guess, not a definitive supplier list. This part is an educated guess assembled by aggregating publicly-available research and institutional-source data — sell-side analyst notes, supplier earnings transcripts, OCP / GTC disclosures, Korean and Taiwanese industry reporting, and primary corporate filings. Vendor relationships, share splits, and revenue allocations across

Vera Rubin Decoded Pt. 5 | Rack Power and the Networking Fabric

Vera Rubin Decoded Pt. 5 | Rack Power and the Networking Fabric

Where to Read What — Series Map Part Title Scope 1 Platform Framing & Architecture Map Blackwell → Rubin platform thesis, headline specs 2 Rubin GPU — Engineering Deep Dive Process node, SMs, HBM4, NVLink-C2C, package, CPX + Groq 3 LPX 3 Vera CPU & the Networking Silicon Family Vera CPU, NVLink 6

Vera Rubin Decoded Pt. 4 | Rack Assembly - Trays, PCB, and Cooling

Vera Rubin Decoded Pt. 4 | Rack Assembly - Trays, PCB, and Cooling

Where to Read What — Series Map Part Title Scope 1 Platform Framing & Architecture Map Blackwell → Rubin platform thesis, headline specs 2 Rubin GPU — Engineering Deep Dive Process node, SMs, HBM4, NVLink-C2C, package, CPX + Groq 3 LPX 3 Vera CPU & the Networking Silicon Family Vera CPU, NVLink 6

Vera Rubin Decoded Pt. 3 | Vera CPU & the Networking Silicon Family

Vera Rubin Decoded Pt. 3 | Vera CPU & the Networking Silicon Family

Where to Read What — Series Map Part Title Scope 1 Platform Framing & Architecture Map Blackwell → Rubin platform thesis, headline specs 2 Rubin GPU — Engineering Deep Dive Process node, SMs, HBM4, NVLink-C2C, package, CPX + Groq 3 LPX 3 Vera CPU & the Networking Silicon Family (this part) Vera CPU,

Vera Rubin Decoded Pt. 2 | Rubin GPU - Engineering Deep Dive

Vera Rubin Decoded Pt. 2 | Rubin GPU - Engineering Deep Dive

Where to Read What — Series Map Part Title Scope 1 Platform Framing & Architecture Map Blackwell → Rubin platform thesis, headline specs 2 Rubin GPU — Engineering Deep Dive (this part) Process node, SMs, HBM4, NVLink-C2C, package, CPX + Groq 3 LPX 3 Vera CPU & the Networking Silicon Family Vera CPU,

Vera Rubin Decoded Pt. 1 | Platform Framing & Architecture Map

Vera Rubin Decoded Pt. 1 | Platform Framing & Architecture Map

Where to Read What — Series Map Part Title Scope 1 Platform Framing & Architecture Map (this part) Blackwell → Rubin platform thesis, headline specs 2 Rubin GPU — Engineering Deep Dive Process node, SMs, HBM4, NVLink-C2C, package, CPX + Groq 3 LPX 3 Vera CPU & the Networking Silicon Family Vera CPU,