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Hot Chips 2026 Day 2 | Memory, Networking, and AI Accelerators

Hot Chips 2026 Day 2 | Memory, Networking, and AI Accelerators

* Day 2 of Hot Chips 2026 centers on the joint design of memory placement, communication, and execution scheduling. * A processor can have ample arithmetic and still wait for a remote weight, an unfinished transfer, a congested link, or another device's result. * The twelve sessions covered here approach those

Hot Chips 2026 Day 1 | CPU and GPU Systems

Hot Chips 2026 Day 1 | CPU and GPU Systems

* Intel, AMD and NVIDIA are competing over a wider part of the computing system. * CPUs are being designed around their role beside accelerators. * GPUs are being designed around memory movement, communication and continued operation through faults. * Delivering more useful work depends on how the processor, memory, software and surrounding system

Hot Chips 2026 Tutorials | Memory

Hot Chips 2026 Tutorials | Memory

* AI infrastructure is becoming harder to improve by increasing arithmetic throughput alone. * The memory tutorials at Hot Chips 2026 examine how capacity, bandwidth, packaging and data movement constrain AI systems. * Memory suppliers are taking on logic, packaging, thermal design and selected computation to keep processors supplied with data. * This article

June 2026 FOMC Minutes Evaluation⎯Inflation, JOLTS Labor Market Signals, and Reserve Balances

June 2026 FOMC Minutes Evaluation⎯Inflation, JOLTS Labor Market Signals, and Reserve Balances

Meeting: June 16–17, 2026 Minutes released July 8, 2026 Statement: * Hold at 3.50–3.75 percent, 12–0 unanimous. * IORB 3.65 percent. * Primary credit rate 3.75 percent. Supplementary data: June 2026 Employment Situation (BLS, released July 2, 2026), FRED, JOLTS. The minutes quantify participant views with

Neoclouds Breakdown

Neoclouds Breakdown

The master note on the neocloud landscape — why the business exists, who the players are, how they finance the fleet, what the compute deals prove, and why Nvidia keeps feeding the ecosystem. 1. Why Neoclouds? (1) The structural gap they fill * The CPU-cloud era was won on software: IaaS

2026 June Wk2 Datacenter Bottleneck(s) Brief

2026 June Wk2 Datacenter Bottleneck(s) Brief

A Cruel Bottleneck's Thesis * On the surface, it was a noisy week. * A SemiAnalysis report on a SOCAMM2 spec downgrade, the scale-up CPO "delay" story, gas-turbine lead-time slips — read off the headlines alone, it is an easy stretch to lose the plot. * The

Datacenter Power Supply Pt. 2 | Bloom's Advantages, 800 VDC, and the Numbers

Datacenter Power Supply Pt. 2 | Bloom's Advantages, 800 VDC, and the Numbers

* Part 2 of 2 — "Datacenter Power Supply." This part covers Bloom Energy's advantages, its 800 VDC fit, the detailed financials and valuation, and the risks. * Part 1 covered the datacenter power-supply bottleneck and the shift to behind-the-meter (BTM) generation, and why fuel cells

Datacenter Power Supply Pt 1 | The Power Bottleneck and the Shift to BTM Fuel Cells

Datacenter Power Supply Pt 1 | The Power Bottleneck and the Shift to BTM Fuel Cells

* Part 1 of 2 — "Datacenter Power Supply." This part covers the datacenter power-supply bottleneck and the shift to behind-the-meter (BTM) generation, and why fuel cells are drawing so much attention here. * Part 2 covers Bloom Energy's advantages, its 800 VDC fit, the detailed

Compute Was Never the Bottleneck — Moving Bits Is

Compute Was Never the Bottleneck — Moving Bits Is

The thesis in one breath * Compute scaled ~60,000× in 20 years; the wires feeding it did not. * The binding constraint on modern AI accelerators is moving bits — and it is one problem whether it happens between GPU↔GPU (the network) or GPU↔memory (the HBM bus), because both cross

Vera Rubin Decoded Pt. 6 | Supply Chain - Master Reference

Vera Rubin Decoded Pt. 6 | Supply Chain - Master Reference

⚠️ Educated guess, not a definitive supplier list. This part is an educated guess assembled by aggregating publicly-available research and institutional-source data — sell-side analyst notes, supplier earnings transcripts, OCP / GTC disclosures, Korean and Taiwanese industry reporting, and primary corporate filings. Vendor relationships, share splits, and revenue allocations across

Vera Rubin Decoded Pt. 5 | Rack Power and the Networking Fabric

Vera Rubin Decoded Pt. 5 | Rack Power and the Networking Fabric

Where to Read What — Series Map Part Title Scope 1 Platform Framing & Architecture Map Blackwell → Rubin platform thesis, headline specs 2 Rubin GPU — Engineering Deep Dive Process node, SMs, HBM4, NVLink-C2C, package, CPX + Groq 3 LPX 3 Vera CPU & the Networking Silicon Family Vera CPU, NVLink 6

Vera Rubin Decoded Pt. 4 | Rack Assembly - Trays, PCB, and Cooling

Vera Rubin Decoded Pt. 4 | Rack Assembly - Trays, PCB, and Cooling

Where to Read What — Series Map Part Title Scope 1 Platform Framing & Architecture Map Blackwell → Rubin platform thesis, headline specs 2 Rubin GPU — Engineering Deep Dive Process node, SMs, HBM4, NVLink-C2C, package, CPX + Groq 3 LPX 3 Vera CPU & the Networking Silicon Family Vera CPU, NVLink 6

Vera Rubin Decoded Pt. 3 | Vera CPU & the Networking Silicon Family

Vera Rubin Decoded Pt. 3 | Vera CPU & the Networking Silicon Family

Where to Read What — Series Map Part Title Scope 1 Platform Framing & Architecture Map Blackwell → Rubin platform thesis, headline specs 2 Rubin GPU — Engineering Deep Dive Process node, SMs, HBM4, NVLink-C2C, package, CPX + Groq 3 LPX 3 Vera CPU & the Networking Silicon Family (this part) Vera CPU,

Vera Rubin Decoded Pt. 2 | Rubin GPU - Engineering Deep Dive

Vera Rubin Decoded Pt. 2 | Rubin GPU - Engineering Deep Dive

Where to Read What — Series Map Part Title Scope 1 Platform Framing & Architecture Map Blackwell → Rubin platform thesis, headline specs 2 Rubin GPU — Engineering Deep Dive (this part) Process node, SMs, HBM4, NVLink-C2C, package, CPX + Groq 3 LPX 3 Vera CPU & the Networking Silicon Family Vera CPU,